Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipation than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power superthreshold computing scheme is proposed to reduce power dissipations of FinFET Domino logic circuits. The pull-down transistors of all FinFET Domino circuits are configured in parallel, and thus improve operating speed. Unlike nearthreshold circuits, super-threshold ones are supplied by much a larger supply voltage than the threshold voltage, but it is lower than the standard supply voltage. Super-threshold FinFET logic circuits can attain low power consumption with favorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS ones. The basic Domino logic gates are compared with static logic ones in terms of energy consumption, delay, energy delay product (EDP), and maximum operation frequency with different voltages from near-threshold to super-threshold regions. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The results show that the Domino gates can operate faster than static ones. In addition, it is also shown that Domino gates exhibit the best EDP in super-threshold regions (about 700mV). Compared with the standard supply voltage of 1.0 V, the Domino gates supplied by 0.8V can attain energy reductions of more than 38.3% with a small performance penalty of about 14%.